By Johan Huijsing, Michiel Steyaert, Arthur H.M. van Roermund
This 10th quantity of "Analog Circuit layout" concentrates on three issues: Scalable Analog Circuits, High-Speed D/A Converters, and RF energy Amplifiers. each one subject is roofed via 6 papers, written via overseas famous specialists on that subject. those papers have an academic nature geared toward bettering the layout of analog circuits. The ebook is split into 3 components: half I, Scalable Analog Circuit layout describes in 6 papers problems with: scalable high-speed layout, scalable high-resolution mixed-mode ADC and OpAmp layout, scalable high-voltage layout for XDSL, scalability of wire-line entrance ends, reusable IP analog layout, and porting CAD analog layout. half II, High-Speed D/A Converters describes in 6 papers problems with: advent to high-speed D/A converter layout, retargetable 12-bit 200-MHz CMOS present steerage layout, high-speed CMOS D/A converters for upstream cable purposes, static and dynamic functionality obstacles, the linearity problem of D/A converters for communications, and a 400-MHz, 10-bit charge-domain CMOS D/A converter for low-spurious frequency synthesis. half III, RF energy Amplifiers describes in 6 papers problems with: method elements, evaluate and trade-offs, linear transmitter architectures, GaAs microwave SSPAs, Monolithic transformer-coupling in Si-bipolar, and RF strength amplifier layout in CMOS. "Analog Circuit layout" is a vital reference resource for analog layout engineers and researchers wishing to maintain abreast with the most recent advancements within the box. the academic insurance additionally makes it appropriate to be used in an boost layout path.
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Additional resources for Analog Circuit Design: Scalable Analog Circuit Design
813-819, Dec. 1984 4) “Architecture and Algorithm for Fully Digital Correction of Monolithic Pipelined ADCs” Soenen and Geiger, IEEE Trans. Circuits and Systems II, Vol. , IEEE Jnl. of Solid State Circuits, Vol. 31, pp. 1862-1872, Dec. 1996 (pumped switches) 6) “Two-phase Bootstrapped CMOS Switch Drive Technique and Circuit” Singer and Brooks, USP 6118326, Sep. 2000 7) “Very Low-Voltage Digital-Audio Delta-Sigma Modulator with 88dB Dynamic Range Using Local Switch Bootstrapping” Dessouky and Kaiser, IEEE Jnl.
Some designers favour only one redundant bit in the whole array, typically around half way down the sequence of bit trials. Others favour perhaps one redundant bit per 4 bits; this latter still allows large errors but only increases the number of bit trials by 5/4. A conceptually elegant alternative which achieves the same result is a successive approximation with an array with slightly less than binary weighting, as in Fig 2c. It will be apparent from inspection that this also allows a search path which converges on the correct result despite moderate errors on the way.
33, pp. 1431-1432, Aug. , Proc. European Solid-State Circuits Conference, Southampton, 1997 20) “Delta-Sigma Data Converters” Norsworthy, Schreier and Temes, IEEE Press, 1997 21) “A Monolithic 19 bits 800kHz Low Power Multibit Sigma Delta Modulator CMOS ADC Using Data Weighted Averaging” Nys and Henderson, Proc. European Solid-State Circuits Conference, pp. 252-255, Southampton, 1996 22) “A Low Oversampling Ratio 14-b 500kHz Delta-Sigma ADC with a Self-Calibrated Multibit DAC” Baird and Fiez, IEEE Jnl.
Analog Circuit Design: Scalable Analog Circuit Design by Johan Huijsing, Michiel Steyaert, Arthur H.M. van Roermund